1. Field of the Invention
The invention relates to a method and related apparatus for adjusting timings of memory signals, and more particularly, to a method and related apparatus of utilizing signals having the same frequency but different phase of a phase locked loop (PLL) to adjust timings of the memory signals.
2. Description of the Prior Art
Computer systems have become one of the most important hardware foundations in today's information society. Therefore, improving the efficiency of computer systems has become a major goal.
As known by those skilled in the art, a computer system comprises a CPU, a memory (such as DRAM), a chipset, etc. The CPU controls the execution of programs and calculation of data and numbers. The above-mentioned data, programs and numbers can be stored in the memory. The chipset is placed between the CPU and the memory for managing the CPU (or other devices of the computer system) to access the memory.
The chipset is electrically connected to the memory through a bus, and controls the data access of the memory through signals of the bus. To control the memory operation timing the chipset has to provide memory clocks to the memory. The chipset has to send command signals in co-ordination with the timing of the memory clocks in order to control the memory to write and/or read data, or to perform other operations such as paging. When the chipset and the memory have to perform a data transmission operation, other signals have to be utilized. For example, when data has to be stored in the memory via the chipset, the chipset not only sends a data signal for transferring data to be stored, but also sends a data indication signal in co-ordination with the timing of the memory clocks to indicate when the memory can receive the data to be stored.
In order to complete the access control of the memory correctly, the above-mentioned signals, including the memory clocks, command signals, data signals, and data indication signals, need to have appropriate timing relationships. For example, the data indication signal can align triggering edges (such as rising edges) of the memory clocks, and these triggering edges of the memory clocks and the data indication signals can trigger the memory to receive the command signals and the data signals between set-up time and hold time.
In real implementations, however, there are many factors which confuse the above-mentioned normal timing relationship. When the chipset has to transfer the electronic signal to the memory, the memory can be regarded as a circuit load of the chipset. This means that different memory arrangements form different circuit loads and further influence the timing of data transmission. In different memory arrangements, the memory connected to the same bus may comprise only one single-inline memory module (SIMM) or comprise two double-inline memory modules (DIMM). For the chipset, the two-DIMM memory arrangement forms a larger circuit load, therefore, when the signal is transferred into the two-DIMM memory, the signal may be delayed more, meaning that signals generated by the chipset to the memory may not have the correct and appropriate timing relationship.
In order to ensure all signals generated by the chipset to the memory do have the correct timing relationship, when the computer system is booting, it performs a timing adjusting operation on all the above-mentioned memory signals generated by the chipset, so as to compensate timing confusion due to non-ideal factors. In the prior art, this timing adjusting operation utilizes different programmable delay lines to inject a corresponding delay time to each memory signal respectively so that memory signals can maintain corresponding timing relationships. For example, if the triggering edge of the data indication signal does not align the triggering edge of the memory clock, the delay line can be utilized to delay the data indication signal so that the delayed data indication signal will properly align the memory clock.
There are some disadvantages in utilizing the delay line, however. The parameters of semiconductor procedures vary (e.g. the doping concentration varies), or the temperature of the system varies (according to location, season or specific operation of the system). These factors may cause the injected delay time of each delay line to vary so that the delay line cannot inject a predetermined delay time and consequently the memory signals will not have correct timing relationships. In general, a programmable delay line can utilize a predetermined delay time td as a unit to selectively delay a signal 1*td, 2*td, 3*td etc. But if the delay time varies, the real injected delay time may be 1*(1−5%)td, 2*(1−5%)td etc. For example, when adjusting timing of the memory signals, if the chipset has to delay a signal k*td so that all signals can have correct timing relationships, the chipset programs a corresponding delay line to delay the signal. But if the characteristic of the delay line varies, the delay line may only inject a k*(1−5%)td time delay. There is an error of k*5%*td which may ruin the timing relationships. Furthermore, different delay lines are used for delaying different signals and the time delay error of these different delay lines may be different. This also confuses the timings of the memory signals. Moreover, the delay line may inject other negative influences (such as a jitter phenomenon) to the signals.